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ASPLOS
2006
ACM
14 years 4 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
CODES
2006
IEEE
14 years 24 days ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
IPPS
1997
IEEE
14 years 3 months ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer
ICA3PP
2010
Springer
14 years 3 months ago
Accelerating Euler Equations Numerical Solver on Graphics Processing Units
Abstract. Finite volume numerical methods have been widely studied, implemented and parallelized on multiprocessor systems or on clusters. Modern graphics processing units (GPU) pr...
Pierre Kestener, Frédéric Chât...
ICIAR
2009
Springer
14 years 3 months ago
VizDraw: A Platform to Convert Online Hand-Drawn Graphics into Computer Graphics
Abstract. With the adoption of tablet-based data entry devices, there is considerable interest in methods for converting hand-drawn sketches of flow charts, graphs and block diagr...
Akshaya Kumar Mishra, Justin A. Eichel, Paul W. Fi...