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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
14 years 2 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
DAC
2008
ACM
14 years 11 months ago
Multiprocessor performance estimation using hybrid simulation
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer L...
PADS
2004
ACM
14 years 3 months ago
Space-Parallel Network Simulations Using Ghosts
We discuss an approach for creating a federated network simulation that eases the burdens on the simulator user that typically arise from more traditional methods for defining sp...
George F. Riley, Talal M. Jaafar, Richard M. Fujim...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 3 months ago
A fast logic simulator using a look up table cascade emulator
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
WSC
2007
14 years 8 days ago
Modeling and simulation of hard disk dive final assembly using a HDD template
A HDD template is designed and developed for modeling and simulation for final assembly of hard disk drive (HDD) manufacturing using Arena. The designed HDD template is a high fle...
Ahad Ali, Robert de Souza