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» Simulation based deadlock analysis for system level designs
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DAC
2006
ACM
14 years 9 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
MOBIWAC
2006
ACM
14 years 2 months ago
Indoor tracking in WLAN location with TOA measurements
Authors presented recently an indoor location technique based on Time Of Arrival (TOA) obtained from Round-Trip-Time (RTT) measurements at data link level and trilateration. This ...
Marc Ciurana, Francisco Barceló, Sebastiano...
WWW
2006
ACM
14 years 9 months ago
Analysis of WWW traffic in Cambodia and Ghana
In this paper we present an analysis of HTTP traffic captured from Internet caf?es and kiosks from two different developing countries ? Cambodia and Ghana. This paper has two main...
Bowei Du, Michael J. Demmer, Eric A. Brewer
ICNP
2005
IEEE
14 years 2 months ago
Efficient Hop ID based Routing for Sparse Ad Hoc Networks
Routing in mobile ad hoc networks remains as a challenging problem given the limited wireless bandwidth, users’ mobility and potentially large scale. Recently, there has been a ...
Yao Zhao, Bo Li, Qian Zhang, Yan Chen, Wenwu Zhu
EOR
2007
85views more  EOR 2007»
13 years 8 months ago
Modeling and analysis of a supply-assembly-store chain
We consider a supply–assembly–store chain with produce-to-stock strategy, which comprises a set of component suppliers, a mixed-model assembly line with a constantly moving co...
Xiaobo Zhao, Deju Xu, Hanqin Zhang, Qi-Ming He