Transistor abstraction for the functional verification of FPGAs

or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdupenlo, tlemeuni, rmayr}@altera.com er discusses the use of transistor abstraction to enable the functional verification of FPGA fabrics with RTL models. It first describes the multiplexer structures that are used on a massive scale in FPGAs and the specific challenges that they pose to or abstraction tools. It then reviews previous approaches and shows that the cone model of the DESB system is particularly ted to abstract FPGA logic because it makes pass-gate branches in multiplexer structures well apparent. Based on this model, methods are described to isolate multiplexer structures, take into account logic correlation between signals, and generate RTL models that are both simulation efficient and highly readable. Finally, Altera's ABX tool that implements these concepts is briefly described. Categorie...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Guy Dupenloup, Thierry Lemeunier, Roland Mayr
• Keywords: DAC 2006, Design Automation, Functional Verification, Multiplexer Structures, Roland Mayr Altera