943 search results - page 15 / 189 » Simulation based deadlock analysis for system level designs |
SUTC
2010
IEEE
13 years 5 months ago
2010
IEEE
—As sensor networks are finding widespread use across many applications, designers increasingly must not only focus on application development, but also on sensor network optimiz...
AIEDU
2006
13 years 7 months ago
2006
In this article, we discuss the motivation for a novel style of tutorial dialogue system that emphasizes reflection in a simulation based exploratory learning environment called Cy...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, a new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of I/O accesses is crucial to performance es...
MEMOCODE
2003
IEEE
14 years 24 days ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...