943 search results - page 33 / 189 » Simulation based deadlock analysis for system level designs |
DATE
2003
IEEE
14 years 27 days ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
WSC
2001
13 years 9 months ago
2001
Discrete-event simulation is a common tool for the analysis of semiconductor manufacturing systems. With the aid of a simulation model, and in conjunction with sensitivity analysi...
ENVSOFT
2006
13 years 7 months ago
2006
We present a set of models for simulating vegetation dynamics in disturbance-prone ecosystems with different complexity levels, integrated in a modelling environment for generatin...
AINA
2007
IEEE
14 years 1 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....