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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 10 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
ICA3PP
2009
Springer
15 years 10 months ago
Reliable Greedy Forwarding in Obstacle-Aware Wireless Sensor Networks
We present Obstacle-aware Virtual Circuit geographic Routing (OVCR), a novel routing mechanism for obstacle-aware wireless sensor networks that uses the obstacle-free path computed...
Ming-Tsung Hsu, Frank Yeong-Sung Lin, Yue-Shan Cha...
IJCNN
2000
IEEE
15 years 10 months ago
Analog Hardware Implementation of the Random Neural Network Model
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
Hossam Abdelbaki, Erol Gelenbe, Said E. El-Khamy
NN
2006
Springer
15 years 5 months ago
Speed-accuracy trade-off in planned arm movements with delayed feedback
The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements...
Dan Beamish, I. Scott MacKenzie, Jianhong Wu
GLVLSI
1997
IEEE
105views VLSI» more  GLVLSI 1997»
15 years 10 months ago
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...
Josef Fleischmann, Rolf Schlagenhaft, Martin Pelle...