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» Simulation of Soliton Circuits
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EH
2003
IEEE
97views Hardware» more  EH 2003»
15 years 11 months ago
Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware
The evolution of circuits with on-line built-in self-test is attempted in simulation for a full adder, a two bit multiplier and an edge triggered D-Latch. Results show that evolve...
Miguel Garvie, Adrian Thompson
ITC
1998
IEEE
82views Hardware» more  ITC 1998»
15 years 10 months ago
A high speed and area efficient on-chip analog waveform extractor
ABSTRACT - A multiple pass A/D conversion technique is proposed for mixed-signal test applications. Only a single on-chip comparator and sample-and-hold circuit is required to digi...
Ara Hajjar, Gordon W. Roberts
DAC
2007
ACM
16 years 6 months ago
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
16 years 9 days ago
Signal Probability Based Statistical Timing Analysis
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
Bao Liu
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
16 years 3 days ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz