1304 search results - page 200 / 261 » Simulation of Soliton Circuits |
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
AAAI
2008
13 years 11 months ago
2008
Automated generators for synthetic models and data can play a crucial role in designing new algorithms/modelframeworks, given the sparsity of benchmark models for empirical analys...
ASPDAC
2008
ACM
13 years 11 months ago
2008
ACM
Abstract-- In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topolo...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...