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IEICET
2007
75views more  IEICET 2007»
13 years 8 months ago
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation with noisy neural elements. Our aim is t...
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshi...
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 3 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ICCAD
1993
IEEE
100views Hardware» more  ICCAD 1993»
14 years 26 days ago
Macromodeling of the A.C. characteristics of CMOS Op-amps
An analytical-knowledge-based statistical method is developed to derive macromodels for the highly nonlinear A.C. response functions of CMOS Op-amp circuits. Simple circuit analys...
Pradip Mandal, V. Visvanathan
SAB
2010
Springer
150views Optimization» more  SAB 2010»
13 years 6 months ago
Internal Models in the Cerebellum: A Coupling Scheme for Online and Offline Learning in Procedural Tasks
The cerebellum plays a major role in motor control. It is thought to mediate the acquisition of forward and inverse internal models of the bodyenvironment interaction [1]. In this ...
Jean-Baptiste Passot, Niceto Luque, Angelo Arleo
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 5 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...