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DAC
2008
ACM
14 years 9 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin
WOSP
1998
ACM
14 years 28 days ago
Poems: end-to-end performance design of large parallel adaptive computational systems
The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runti...
Ewa Deelman, Aditya Dube, Adolfy Hoisie, Yong Luo,...
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
14 years 9 months ago
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications
In this paper, we have studied and compared the RF performance metrics, unity gain frequency (ft) and Noise Figure (NF), of the devices with channel engineering consisting of halo...
R. Srinivasan, Navakanta Bhat
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
14 years 9 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
14 years 2 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman