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DAC
1997
ACM
13 years 11 months ago
Technology-Dependent Transformations for Low-Power Synthesis
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
Rajendran Panda, Farid N. Najm
IPPS
1999
IEEE
13 years 11 months ago
The Impact of Memory Hierarchies on Cluster Computing
Using off-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform ...
Xing Du, Xiaodong Zhang
CODES
2004
IEEE
13 years 11 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
HAIS
2009
Springer
14 years 4 days ago
Economic Load Dispatch Using a Chemotactic Differential Evolution Algorithm
This paper presents a novel stochastic optimization approach to solve constrained economic load dispatch (ELD) problem using Hybrid Bacterial Foraging-Differential Evolution optimi...
Arijit Biswas, Sambarta Dasgupta, Bijaya K. Panigr...
PPOPP
2006
ACM
14 years 1 months ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...