Central pattern generators (CPGs) have traditionally been modeled as sets of coupled bistable oscillators [2]. We present a framework for constructing models which avoid the short...
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Neurons in area V4 have relatively large receptive fields (RFs), so multiple visual features are simultaneously "seen" by these cells. Recordings from single V4 neurons ...
We give some new Wilf equivalences for signed patterns which allow the complete classification of signed patterns of lengths three and four. The problem is considered for pattern a...
W. M. B. Dukes, Toufik Mansour, Astrid Reifegerste
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...