65 search results - page 9 / 13 » Simultaneous Circuit Transformation and Routing |
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
TCAD
2008
13 years 7 months ago
2008
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for ...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...