78 search results - page 13 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
MICRO
2002
IEEE
13 years 7 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
— We consider a dense fading multi-user network with multiple active multi-antenna source-destination pair terminals communicating simultaneously through a large common set of K ...