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    FPGA
    2008
    ACM
    151views FPGA» more  FPGA 2008»
    Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
    13 years 11 months ago
    Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
    Download  www3.ee.iastate.edu
    Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
    Michael T. Frederick, Arun K. Somani
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    DAC
    2003
    ACM
    129views Computer Architecture» more  DAC 2003»
    A new enhanced constructive decomposition and mapping algorithm
    14 years 10 months ago
    A new enhanced constructive decomposition and mapping algorithm
    Download  www.eecs.berkeley.edu
    Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
    Alan Mishchenko, Xinning Wang, Timothy Kam
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    FPGA
    2008
    ACM
    184views FPGA» more  FPGA 2008»
    Mapping for better than worst-case delays in LUT-based FPGA designs
    13 years 11 months ago
    Mapping for better than worst-case delays in LUT-based FPGA designs
    Download  cadlab.cs.ucla.edu
    Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
    Kirill Minkovich, Jason Cong
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    FPGA
    2006
    ACM
    113views FPGA» more  FPGA 2006»
    Optimality study of logic synthesis for LUT-based FPGAs
    14 years 1 months ago
    Optimality study of logic synthesis for LUT-based FPGAs
    Download  cadlab.cs.ucla.edu
    Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
    Jason Cong, Kirill Minkovich
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    ICCAD
    2007
    IEEE
    164views Hardware» more  ICCAD 2007»
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    14 years 6 months ago
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    Download  www.ee.ucla.edu
    — Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
    Yu Hu, Satyaki Das, Steven Trimberger, Lei He
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