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SIROCCO
2004
13 years 10 months ago
Two-Hop Virtual Path Layout in Tori
We consider a problem motivated by the design of ATM (Asynchronous Transfer Mode) networks. Given a physical network and an All-to-All traffic, the problem consists in designing a...
Sébastien Choplin, Lata Narayanan, Jaroslav...
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
14 years 2 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
INFOCOM
2005
IEEE
14 years 2 months ago
Improving VoIP quality through path switching
Abstract— The current best-effort Internet cannot readily provide the service guarantees that VoIP applications often require. Path switching can potentially address this problem...
Shu Tao, Kuai Xu, Antonio Estepa, Teng Fei, Lixin ...
CORR
2010
Springer
162views Education» more  CORR 2010»
13 years 9 months ago
Random sampling of lattice paths with constraints, via transportation
We investigate Monte Carlo Markov Chain (MCMC) procedures for the random sampling of some one-dimensional lattice paths with constraints, for various constraints. We will see that...
Lucas Gerin
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
14 years 1 months ago
A timing analysis algorithm for circuits with level-sensitive latches
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong