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PATMOS
2007
Springer
15 years 9 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
128
Voted
ICRA
2006
IEEE
137views Robotics» more  ICRA 2006»
15 years 9 months ago
Fast C-obstacle Query Computation for Motion Planning
— The configuration space of a robot is partitioned into free space and C-obstacle space. Most of the prior work in collision detection and motion planning algorithms is targete...
Liangjun Zhang, Young J. Kim, Gokul Varadhan, Dine...
104
Voted
INFOCOM
2006
IEEE
15 years 9 months ago
Tunnel Vector: A New Routing Algorithm with Scalability
—Routing algorithms such as Distance Vector and Link States have the routing table size as ΩΩΩΩ (n), where n is the number of destination identifiers, thus providing only...
Cheng-Jia Lai, Richard R. Muntz
130
Voted
INFOCOM
2006
IEEE
15 years 9 months ago
Mobile Emulab: A Robotic Wireless and Sensor Network Testbed
Abstract— Simulation has been the dominant research methodology in wireless and sensor networking. When mobility is added, real-world experimentation is especially rare. However,...
David Johnson, Tim Stack, Russ Fish, Daniel Montra...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
15 years 9 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang