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HPCA
2009
IEEE
14 years 8 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
HPCA
2011
IEEE
12 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
IEEEPACT
2005
IEEE
14 years 1 months ago
Trace Cache Sampling Filter
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
Michael Behar, Avi Mendelson, Avinoam Kolodny
ISCA
2008
IEEE
142views Hardware» more  ISCA 2008»
14 years 2 months ago
Improving NAND Flash Based Disk Caches
Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable spe...
Taeho Kgil, David Roberts, Trevor N. Mudge
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
14 years 2 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras