155 search results - page 28 / 31 » Soft delay error analysis in logic circuits |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
SLIP
2003
ACM
14 years 27 days ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
FDTC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...