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GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 20 days ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
EDOC
2007
IEEE
14 years 2 months ago
Modeling and Integrating Aspects into Component Architectures
Dependable software systems are difficult to develop because developers must understand and address several interdependent and pervasive dependability concerns. Features that addr...
Lydia Michotte, Robert B. France, Franck Fleurey
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 9 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
FTCS
1996
110views more  FTCS 1996»
13 years 9 months ago
Experimental Assessment of Parallel Systems
In the research reported in this paper, transient faults were injected in the nodes and in the communication subsystem (by using software fault injection) of a commercial parallel...
João Gabriel Silva, Joao Carreira, Henrique...
SARA
2009
Springer
14 years 2 months ago
Automated Redesign with the General Redesign Engine
: Given a system design (SD), a key task is to optimize this design to reduce the probability of catastrophic failures. We consider the task of redesigning an SD to minimize the pr...
Alexander Feldman, Gregory M. Provan, Johan de Kle...