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CASES
2007
ACM
13 years 12 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
CGO
2004
IEEE
13 years 11 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
CLEF
2006
Springer
13 years 11 months ago
TALP at GeoCLEF 2006: Experiments Using JIRS and Lucene with the ADL Feature Type Thesaurus
This paper describes our experiments in Geographical Information Retrieval (GIR) in the context of our participation in the GeoCLEF 2006 Monolingual English task. The TALPGeoIR sy...
Daniel Ferrés, Horacio Rodríguez
ISPASS
2010
IEEE
13 years 10 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
SSR
2001
73views more  SSR 2001»
13 years 9 months ago
XML implementation of frame processor
A quantitative study has shown that frame technology [1] supported by Fusion toolset can lead to reduction in time-tomarket (70%) and project costs (84%). Frame technology has bee...
Tak Wong, Stan Jarzabek, Soe Myat Swe, Ru Shen, Ho...