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CASES
2005
ACM
13 years 10 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
ISPASS
2008
IEEE
14 years 2 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 8 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 8 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
PODC
2009
ACM
14 years 8 months ago
Bounding the locality of distributed routing algorithms
d Abstract] Prosenjit Bose School of Computer Science Carleton University Ottawa, Canada jit@scs.carleton.ca Paz Carmi Dept. of Computer Science Ben-Gurion Univ. of the Negev Beer-...
Prosenjit Bose, Paz Carmi, Stephane Durocher