39 search results - page 8 / 8 » Software Pipelining for Coarse-Grained Reconfigurable Instru... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
EUROSYS
2010
ACM
14 years 4 months ago
2010
ACM
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...