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IPPS
2000
IEEE
14 years 3 months ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy
CGO
2003
IEEE
14 years 2 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
VLSID
2003
IEEE
123views VLSI» more  VLSID 2003»
14 years 11 months ago
Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling
A formal synthesis method for complex real-time embedded software is proposed in this work. Compared to previous work, our method not only synthesizes embedded software with compl...
Pao-Ann Hsiung, Feng-Shi Su
CODES
2001
IEEE
14 years 2 months ago
Formal synthesis and code generation of embedded real-time software
Due to rapidly increasing system complexity, shortening time-tomarket, and growing demand for hard real-time systems, formal methods are becoming indispensable in the synthesis of...
Pao-Ann Hsiung
ICST
2010
IEEE
13 years 9 months ago
Does Hardware Configuration and Processor Load Impact Software Fault Observability?
Intermittent failures and nondeterministic behavior complicate and compromise the effectiveness of software testing and debugging. To increase the observability of software faults,...
Raza Abbas Syed, Brian Robinson, Laurie A. William...