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LCPC
2005
Springer
14 years 3 months ago
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Ro...
CASES
2004
ACM
14 years 3 months ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
PLDI
2004
ACM
14 years 3 months ago
Region inference for an object-oriented language
Region-based memory management offers several important potential advantages over garbage collection, including real-time performance, better data locality, and more efficient us...
Wei-Ngan Chin, Florin Craciun, Shengchao Qin, Mart...
ICPP
2003
IEEE
14 years 3 months ago
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
Xiaotong Zhuang, Hsien-Hsin S. Lee
CCGRID
2002
IEEE
14 years 3 months ago
Overcoming the Problems Associated with the Existence of Too Many DSM APIs
Despite the large research efforts in the SW–DSM community, this technology has not yet been adapted widely for significant codes beyond benchmark suites. One of the reasons co...
Martin Schulz