Sciweavers

2512 search results - page 428 / 503
» Software Transactional Memory
Sort
View
DAC
2008
ACM
15 years 4 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
BCS
2008
15 years 3 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton
ECRTS
2010
IEEE
15 years 3 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
EUROPAR
2010
Springer
15 years 3 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
AI
2007
Springer
15 years 2 months ago
An algorithm for distributing coalitional value calculations among cooperating agents
The process of forming coalitions of software agents generally requires calculating a value for every possible coalition which indicates how beneficial that coalition would be if...
Talal Rahwan, Nicholas R. Jennings