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ISCAPDCS
2003
13 years 8 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
ICCD
2007
IEEE
139views Hardware» more  ICCD 2007»
14 years 4 months ago
Statistical simulation of chip multiprocessors running multi-program workloads
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
Davy Genbrugge, Lieven Eeckhout
SIGCOMM
2006
ACM
14 years 1 months ago
Planet scale software updates
Fast and effective distribution of software updates (a.k.a. patches) to millions of Internet users has evolved into a critical task over the last years. In this paper, we characte...
Christos Gkantsidis, Thomas Karagiannis, Milan Voj...
ICPADS
1994
IEEE
13 years 11 months ago
Delayed Precise Invalidation - A Software Cache Coherence Scheme
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
T.-S. Hwang, C.-P. Chung
SIGGRAPH
1997
ACM
13 years 11 months ago
Rendering complex scenes with memory-coherent ray tracing
Simulating realistic lighting and rendering complex scenes are usually considered separate problems with incompatible solutions. Accurate lighting calculations are typically perfo...
Matt Pharr, Craig E. Kolb, Reid Gershbein, Pat Han...