Sciweavers

1406 search results - page 213 / 282
» Software trace cache
Sort
View
CASES
2007
ACM
13 years 11 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...
HOTOS
2009
IEEE
13 years 11 months ago
An End to the Middle
The last fifteen years has seen a vast proliferation of middleboxes to solve all manner of persistent limitations in the Internet protocol suite. Examples include firewalls, NATs,...
Colin Dixon, Arvind Krishnamurthy, Thomas E. Ander...
CODES
2004
IEEE
13 years 11 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
EUROSYS
2006
ACM
13 years 11 months ago
TCP offload through connection handoff
This paper presents a connection handoff interface between the operating system and the network interface. Using this interface, the operating system can offload a subset of TCP c...
Hyong-youb Kim, Scott Rixner
CASES
2001
ACM
13 years 11 months ago
Efficient longest executable path search for programs with complex flows and pipeline effects
Current development tools for embedded real-time systems do not efficiently support the timing aspect. The most important timing parameter for scheduling and system analysis is th...
Friedhelm Stappert, Andreas Ermedahl, Jakob Engblo...