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RTAS
2008
IEEE
14 years 2 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
CSMR
2005
IEEE
14 years 1 months ago
Correlating Features and Code Using a Compact Two-Sided Trace Analysis Approach
Software developers are constantly required to modify and adapt application features in response to changing requirements. The problem is that just by reading the source code, it ...
Orla Greevy, Stéphane Ducasse
EUROMICRO
2003
IEEE
14 years 27 days ago
Polishing: A Technique to Reduce Variations in Cached Layer-Encoded Video
In this paper we present polishing, a novel technique to maximize the playback utility of a streamed layer-encoded video. Polishing reduces the amount of layer variations in a cac...
Michael Zink, Oliver Heckmann, Jens Schmitt, Andre...
JPDC
2010
106views more  JPDC 2010»
13 years 6 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
IPPS
2003
IEEE
14 years 27 days ago
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Dennis Abts, Steve Scott, David J. Lilja