596 search results - page 37 / 120 » Software transactional memory for multicore embedded systems |
COMPSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
The conflicting requirements of real-time embedded systems, e.g. minimizing memory usage while still ensuring that all deadlines are met at run-time, require rigorous analysis of...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
FAST
2008
2008
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling
13 years 8 months ago
In this paper we develop a recovery conscious framework for multi-core architectures and a suite of techniques for improving the resiliency and recovery efficiency of highly conc...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...