67 search results - page 7 / 14 » Software-based instruction caching for embedded processors |
RTCSA
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
ISCA
2003
IEEE
14 years 23 days ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...