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FMCAD
2004
Springer
13 years 11 months ago
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis
This work presents a memory-efficient All-SAT engine which, given a propositional formula over sets of important and non-important variables, returns the set of all the assignments...
Orna Grumberg, Assaf Schuster, Avi Yadgar
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
14 years 4 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
AIPS
2000
13 years 8 months ago
Investigating the Effect of Relevance and Reachability Constraints on SAT Encodings of Planning
Currently, Graphplan and Blackbox, which converts Graphplan's plan graph into the satisfaction (SAT) problem, are two of the most successful planners. Since Graphplan gains i...
Minh Binh Do, Biplav Srivastava, Subbarao Kambhamp...
IFIP
2001
Springer
13 years 12 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
13 years 12 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann