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SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
14 years 4 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
AMFG
2005
IEEE
181views Biometrics» more  AMFG 2005»
14 years 3 months ago
An Integrated Two-Stage Framework for Robust Head Pose Estimation
Abstract. Subspace analysis has been widely used for head pose estimation. However, such techniques are usually sensitive to data alignment and background noise. In this paper a tw...
Junwen Wu, Mohan M. Trivedi
CGO
2005
IEEE
14 years 3 months ago
Reactive Techniques for Controlling Software Speculation
Aggressive software speculation holds significant potential, because it enables program transformations to reduce the program’s critical path. Like any form of speculation, how...
Craig B. Zilles, Naveen Neelakantam
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 3 months ago
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration
— Balanced truncation (BT) model order reduction (MOR) is known for its superior accuracy and computable error bounds. Balanced stochastic truncation (BST) is a particular BT pro...
Ngai Wong, Venkataramanan Balakrishnan
IPPS
2005
IEEE
14 years 3 months ago
MaTCH : Mapping Data-Parallel Tasks on a Heterogeneous Computing Platform Using the Cross-Entropy Heuristic
We propose in this paper a heuristic for mapping a set of interacting tasks of a parallel application onto a heterogeneous computing platform such as a computational grid. Our nov...
Soumya Sanyal, Sajal K. Das