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» Sorting and Selection on Distributed Memory Bus Computers
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EUROPAR
2009
Springer
13 years 11 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
SDM
2009
SIAM
119views Data Mining» more  SDM 2009»
14 years 4 months ago
Twin Vector Machines for Online Learning on a Budget.
This paper proposes Twin Vector Machine (TVM), a constant space and sublinear time Support Vector Machine (SVM) algorithm for online learning. TVM achieves its favorable scaling b...
Zhuang Wang, Slobodan Vucetic
ISORC
2009
IEEE
14 years 2 months ago
Embedded JIT Compilation with CACAO on YARI
Java is one of the most popular programming languages for the development of portable workstation and server applications available today. Because of its clean design and typesafe...
Florian Brandner, Tommy Thorn, Martin Schoeberl
ASPLOS
1994
ACM
13 years 11 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
HPCA
2006
IEEE
14 years 7 months ago
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg