354 search results - page 35 / 71 » Sorting networks on FPGAs |
IPPS
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
FPL
2006
Springer
14 years 2 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
ASPDAC
2001
ACM
14 years 2 months ago
2001
ACM
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
ASPDAC
2005
ACM
14 years 29 days ago
2005
ACM
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...
IESS
2007
Springer
14 years 5 months ago
2007
Springer
This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous node...