Sciweavers

354 search results - page 40 / 71
» Sorting networks on FPGAs
Sort
View
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
14 years 5 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 5 months ago
Optimization of regular expression pattern matching circuits on FPGA
Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to ...
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang,...
FPL
2009
Springer
161views Hardware» more  FPL 2009»
14 years 3 months ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
ISCC
2009
IEEE
262views Communications» more  ISCC 2009»
14 years 5 months ago
Babelchord: a social tower of DHT-based overlay networks
Chord is a protocol to distribute and retrieve information at large scale. It builds a large but rigid overlay network without taking into account the social nature and the underl...
Luigi Liquori, Cédric Tedeschi, Francesco B...
IPPS
2007
IEEE
14 years 5 months ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri