87 search results - page 2 / 18 » Space of DRAM fault models and corresponding testing |
ATS
2003
IEEE
14 years 20 days ago
2003
IEEE
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
DFT
2002
IEEE
14 years 9 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
LADC
2007
Springer
14 years 1 months ago
2007
Springer
PAMI
2008
13 years 7 months ago
2008
This paper introduces a new benchmark study to evaluate the performance of landmark-based shape correspondence used for statistical shape analysis. Different from previous shape-co...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...