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» Space of DRAM fault models and corresponding testing
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TC
1998
13 years 7 months ago
Optimal Zero-Aliasing Space Compaction of Test Responses
—Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The ...
Krishnendu Chakrabarty, Brian T. Murray, John P. H...
TAICPART
2010
IEEE
158views Education» more  TAICPART 2010»
13 years 5 months ago
Bad Pairs in Software Testing
Abstract. With pairwise testing, the test model is a list of N parameters. Each test case is an N-tuple; the test space is the cross product of the N parameters. A pairwise test is...
Daniel Hoffman, Chien Chang, Gary Bazdell, Brett S...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
14 years 20 days ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
PTS
1993
106views Hardware» more  PTS 1993»
13 years 8 months ago
Generating Synchronizable Test Sequences Based on Finite State Machine with Distributed Ports
In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several t...
Gang Luo, Rachida Dssouli, Gregor von Bochmann, Pa...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 19 days ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...