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HPCA
2008
IEEE
14 years 8 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
ICALP
2009
Springer
14 years 8 months ago
LTL Path Checking Is Efficiently Parallelizable
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
Lars Kuhtz, Bernd Finkbeiner
HICSS
2010
IEEE
185views Biometrics» more  HICSS 2010»
14 years 2 months ago
Concurrent Architecture for Automated Malware Classification
This paper introduces a new architecture for automating the generalization of program structure and the recognition of common patterns in the area of malware analysis. By using ma...
Timothy Daly, Luanne Burns
PLDI
2009
ACM
14 years 2 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
WECWIS
2009
IEEE
104views ECommerce» more  WECWIS 2009»
14 years 2 months ago
Online Auctions: There Can Be Only One
—In recent years, the proliferation of the world wide web has lead to an increase in the number of public auctions on the internet. One of the characteristics of online auctions ...
Charu C. Aggarwal, Philip S. Yu