The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
We discuss an approach for creating a federated network simulation that eases the burdens on the simulator user that typically arise from more traditional methods for defining sp...
George F. Riley, Talal M. Jaafar, Richard M. Fujim...
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
We present a new run-time system for typed programming languages that supports object sharing in a distributed system. The key insight in this system is that the ability to distin...
Y. Charlie Hu, Weimin Yu, Alan L. Cox, Dan S. Wall...
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...