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ICCAD
2004
IEEE
94views Hardware» more  ICCAD 2004»
14 years 4 months ago
Timing macro-modeling of IP blocks with crosstalk
With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must b...
Ruiming Chen, Hai Zhou
TCOM
2010
63views more  TCOM 2010»
13 years 2 months ago
Efficiently decoded full-rate space-time block codes
Space-time block codes with orthogonal structures typically provide full-diversity reception and simple receiver processing. However, rate-1 orthogonal codes for complex constellat...
Don J. Torrieri, Matthew C. Valenti
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
13 years 11 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
CCE
2008
13 years 7 months ago
Population balance modeling in Simulink: PCSS
In this work we develop, demonstrate, and distribute the code for a new Simulink block that models the dynamic evolution of the population density function for a physical system w...
Jeffrey D. Ward, Cheng-Ching Yu
DATE
2007
IEEE
56views Hardware» more  DATE 2007»
14 years 1 months ago
Unknown blocking scheme for low control data volume and high observability
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar