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» Specify, Compile, Run: Hardware from PSL
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HICSS
1997
IEEE
120views Biometrics» more  HICSS 1997»
13 years 11 months ago
Building the 4 Processor SB-PRAM Prototype
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
Peter Bach, Michael Braun, Arno Formella, Jör...
MTV
2005
IEEE
100views Hardware» more  MTV 2005»
14 years 1 months ago
A Study of Architecture Description Languages from a Model-based Perspective
Abstract— Owing to the recent trend of using applicationspecific instruction-set processors (ASIP), many Architecture Description Languages (ADLs) have been created. They specif...
Wei Qin, Sharad Malik
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 2 months ago
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent function...
Trevor Meyerowitz, Alberto L. Sangiovanni-Vincente...
SAC
2010
ACM
13 years 9 months ago
Reactive parallel processing for synchronous dataflow
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
Claus Traulsen, Reinhard von Hanxleden
ISSTA
1993
ACM
13 years 11 months ago
Mutation Analysis Using Mutant Schemata
Mutation analysis is a powerful technique for assessing and improving the quality of test data used to unit test software. Unfortunately, current automated mutation analysis syste...
Roland H. Untch, A. Jefferson Offutt, Mary Jean Ha...