Sciweavers

104 search results - page 3 / 21
» Specify, Compile, Run: Hardware from PSL
Sort
View
FPL
2003
Springer
259views Hardware» more  FPL 2003»
14 years 22 days ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
HPCA
2012
IEEE
12 years 3 months ago
Pacman: Tolerating asymmetric data races with unintrusive hardware
Data races are a major contributor to parallel software unreliability. A type of race that is both common and typically harmful is the Asymmetric data race. It occurs when at leas...
Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira...
ERSA
2006
186views Hardware» more  ERSA 2006»
13 years 9 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
ICALP
2009
Springer
14 years 7 months ago
LTL Path Checking Is Efficiently Parallelizable
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
Lars Kuhtz, Bernd Finkbeiner
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 11 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli