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ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
APCSAC
2001
IEEE
13 years 11 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
CGO
2006
IEEE
14 years 1 months ago
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework
Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However, to be effective, prefetching must target the most critical (frequently...
Weifeng Zhang, Brad Calder, Dean M. Tullsen
ICC
2009
IEEE
135views Communications» more  ICC 2009»
13 years 5 months ago
Load Aware Broadcast in Mobile Ad Hoc Networks
In a wireless ad hoc network, the main issue of a good broadcast protocol is to attain maximum reachability with minimal packet forwarding. Existing protocols address this issue by...
Md. Tanvir Al Amin, Sukarna Barua, Sudip Vhaduri, ...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 7 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....