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» Speculative Computation in Multilisp
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VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 8 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
ASPLOS
2006
ACM
14 years 2 months ago
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkate...
EUROPAR
2005
Springer
14 years 2 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
LCPC
2004
Springer
14 years 1 months ago
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei...
MICRO
2000
IEEE
118views Hardware» more  MICRO 2000»
14 years 26 days ago
A study of slipstream processors
A slipstream processor reduces the length of a running program by dynamically skipping computation non-essential for correct forward progress. The shortened program runs faster as...
Zachary Purser, Karthik Sundaramoorthy, Eric Roten...