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ISBI
2007
IEEE
14 years 1 months ago
Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
KBSE
2007
IEEE
14 years 1 months ago
Testing concurrent programs using value schedules
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...
Jun Chen, Steve MacDonald
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
IEEEPACT
2005
IEEE
14 years 1 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
IEEEPACT
2005
IEEE
14 years 1 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...