Sciweavers

723 search results - page 54 / 145
» Speculative Dynamic Vectorization
Sort
View
KBSE
2007
IEEE
15 years 9 months ago
Testing concurrent programs using value schedules
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...
Jun Chen, Steve MacDonald
117
Voted
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 8 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
15 years 8 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
131
Voted
MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
15 years 7 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
127
Voted
ICS
1999
Tsinghua U.
15 years 7 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...