122 search results - page 13 / 25 » Speculative Parallel Threading Architecture and Compilation |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
MICRO
1993
IEEE
13 years 12 months ago
1993
IEEE
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelism ILP found in non-numeric programs. An importantpr...
ISPDC
2008
IEEE
14 years 2 months ago
2008
IEEE
In this work we present the runtime architecture of the OMPi OpenMP compiler. OMPi is a source-to-source C translator featuring a portable, modular and extensible runtime system. ...