122 search results - page 18 / 25 » Speculative Parallel Threading Architecture and Compilation |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
APCSAC
2003
IEEE
13 years 11 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
CGO
2008
IEEE
14 years 2 months ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...